(--
    'SAMIPS.balsa'
     The Top level control process for the SAMIPS architecture  with precise exceptions 
       
     Jan 2004
--)

-- include five stages

import [IF]
import [ID]
import [EX]
import [MEM]
import [WB]
import [CP0]
import [InsMemory]
import [DataMemory]

-- input/output channel is the interface to memory

procedure SAMIPS 

is channel CIns     : CIns
   channel CInsAdd  : InsAdd
   channel WriteData: MemWord
   channel DataAdd  : MemAdd
   channel IDch, EXch, NTarget2 : ch
   channel MEMch    : MEMch
   channel RegWrite : RegWrite
   channel EXCtrl   : EXCtrl
   channel BaseAddEX:BaseAddEX
   channel BaseAddID, BaseAddMEM, ReadData0, ReadData1, CP0RegData:word
   channel FEXRes,  FMEMRes, MemData, Offset32, EXRes, MEMRes, MemD: word
   channel IDRd, EXRd : CHRd
   channel MEMRd    : Rd
   channel MEMCtrl  : MEMCtrl
   channel WBCtrl   : WB
   channel sa       : 5 bits
   channel FWCtrl   : FWCtrl
   channel FRACtrl  : FRACtrl
   channel RegRead  : RegRead
   channel CP0W2, CP0W1 : CP0Write
   channel CP0R         : RegNo 
   channel start        : bit
begin
  IF  (start, IDch, EXch, MEMch, BaseAddID, CInsAdd, CP0W2) ||
  ID  (BaseAddID, RegWrite, CIns, 
       EXCtrl, sa, ReadData0, ReadData1, Offset32, 
       BaseAddEX, IDRd, CP0R, IDch, FWCtrl, FRACtrl) ||
  EX  (EXCtrl, FWCtrl, FRACtrl, sa, IDRd, ReadData0, ReadData1, 
       FEXRes, FMEMRes, Offset32, CP0RegData, BaseAddEX, 
       EXRes, MemD, BaseAddMEM, MEMCtrl, EXch, EXRd) ||
  MEM (MEMCtrl, EXRes, MemD, BaseAddMEM, MemData, EXRd, 
       MEMRd, WBCtrl, DataAdd, WriteData, MEMRes, FEXRes, MEMch) ||
  WB  (WBCtrl, MEMRd, MEMRes, RegWrite, CP0W1, FMEMRes) ||
  CP0 ( CP0R, CP0W1, CP0W2, CP0RegData) ||
  InsMemory (CInsAdd, CIns, start) ||
  DataMemory(DataAdd, WriteData, MemData)
end 