*************
** WrtCtrl **
*************

Messages from the DataInt arrive as a result of LDR and LDM instructions.

1. In the case of LDR:
-------------------

A message with the data address arrives to the WrtCtrl 
from the ALU and from there it is sent to AddC.
A new entry is inserted into the lookahead table
for the expected data. If the instruction aborts
the data will arrive anyway from the memory although it will
be invalid. Therefore no special functionality is required
to deal with aborts in this case. The operation continues as normal.

2. In the case of LDM
-------------------

The program driven algorithm is based on the
assumption that there is a regular flow of
messages on one input channel and messages to the other will 
arrive occasionally as a result of the former.
In the case of an LDM, a message from the ALU 
will result in a number of messages which will
arrive from the memory. This number is the number of the
registers specified in the register list of the LDM instruction.

If the WrtCtrl blocks waiting for a message from the ALU before it 
process a message (LDM data) which has arrived from memory, a deadlock
will occur since the ALU will send NO messages until the loading
of the registers has been completed ie the messages from the memory have
been processed by WrtCtrl. 

Therefore, in the case of an LDM, WrtCtrl consumes *a number* of 
messages from the memory before it waits for a message from the ALU.

Question: What is the value of this number, above???

This value can be decided if the behaviour of the LDM instruction
with regards to aborts is examined. 

The path: 

AddC---> DatInt(MemCtrl)---> Memory--->DatInt(DestCtrl)--->WrtCtrl

has 3 registers, 1 (MAR) before the memory and 2 (MRR, Din) after it.

*If an abort does not occur*
-----------------------------
during the execution of the LDM instruction
then when the *last* data address reaches memory, memory will send a 
abort0 signal to the ALU. From that point the ALU is free to produce
more messages. 

WrtCtrl should accept and consume so many messages from memory
so as to let the *last* data address to reach memory.

Since there are 2 registers(stages) between memory and WrtCtrl,
if N is the number of registers in the register list of 
the LDM and Wrtctrl consumes less than N-2 messages before it blocks
the last message will never arrive in memory, therefore the abort0 signal
will never be produced by memory and the system will deadlock. 

If on the other hand, WrtCtrl consumes *more* than N-2 messages before it blocks
waiting for ALU messages, a preemption migh occur!!:
With the (N-2)th message accepted by the WrtCtrl, the *last* data
address arrives to memory which produces the abort0 signal to the ALU.
The ALU then is free to send a new message to WrtCtrl. This ALU message
might arrive to WrtCtrl before the (N-1) message form memory and if WrtCtrl
is blocked reading messages from memory and reads the (N-1)th before
seeing the message from ALU a preemption will occur.!- 

Conclusion: If an abort does not occur, then before the consumption of the
(N-2)th message by the WrtCtrl NO message will be sent from the ALU, however,
after that point an ALU message might arrive at any time!!! 

Another point that should be taken into account is the second cycle of the
LDM instruction, where a writeback to the base register is performed,
ie a message arrives from the ALU immediately after the base address.
We assume that this message will arrive *before* data start arriving from
memory. (I need to check for preemptions here!!!). 

So we end up with the following algorithm:

 .read a message from ALU
  IF
    LDM
      .let the message through in the usual way
      .read yet another message and let it through
      .append two entries(for the last 2 messages) in the lookahead table
       .FOR I=0 TO N-2
          .read message from Din
          .let message through
 .continue normal operation-main loop
     

*If an abort does occur*
--------------------------
during the execution of the LDM instruction
then this may happen at any point during the third cycle
of the instruction (data tranfers).  

This will have no effect regarding deadlocks, since *all* the 
expected data from memory wiil arrive, although they will be invalid.
When an abort occurs, the memory sends an abort1 signal to the ALU
and from that point the ALU is free to send messages 
to WrtCtrl.  If however WrtCtrl waits for the N-2 messages from the memory
before it allows a message from the ALU through, and an abort
happens, say during the 3rd memory access(read), then preemptions
will take place.

Therefore, WrtCtrl needs to know if an abort has occured or not
for each one of the data tranfers. 

Question: How can this be achieved?? 

One solution might be to check the value of the valid bit
for each  message that arrives from memory. If the message
is invalid then WrtCtrl know that an abort has occured and 
exits from the loop above, allowing messages from the ALU through.
However this technique does not guarantee that a preemption will not occur.
This is due to the fact that *the abort1 signal might arrive to the ALU
(and consequently the new message from the ALU to WrtCtrl) before the 
corresponding invalid data arrives to WrtCtrl*. 

Question: Although the above may be generally true, the fact
is that the ALU will produce a message to the WrtCtrl
as a result of a message that it gets from the blocks before it.
However once the third cycle (data tranfers)of the instruction strarts
NO event will be sent from the Dec1 down tha path to the ALU.
And thus no event will be generated by the ALU as a result of a 
message from the ALU before such a message is actually produced by the Dec1!!!!!
So, even if an abort takes place, a message from the ALU to the WrtCtrl will be sent
only after the completion of the data transfers!!! 

Therefore the algorithm above  is sufficient for the case
of aborts as well!!!!!   .-

3. DEADLOCKS:
--------------
3.1  DUE TO PIPE STALL:  

A pipeline may stall and therefore no message will arrive to WrtCtrl 
if 

a) An LDM instruction is executing and the pipe has been blocked at the Dec1.
   This case has been tackled in the preceding sections.

b) A read register instruction is executing waiting for the register
   to be written by the data that is being held by WrtCtrl!!! 
   WrtCtrl should somehow be informed of this fact and let the data
   through without  waiting for a message from ALU.  
   We note that Ctrl3 is free to consume messages coming from the datapath
   since it has received the abort signal. So both valid and invalid 
   data are treated the same in that sense. So we need a machanism to
   inform WrtCtrl that RegBank is locked....Note that if Reg Bank is locked
   and a read reg instruction waits there, all subsequent instructions will 
   block and no further messages will arrive (is this true??? I think it is).

   The solution here is the following:
   



If a data  to be written to a register has been received by  WrtCtrl,
wrtctrl








3.2  DUE TO PIPE EMPTY:
 


 











 


   

 



  





 
