
#INCLUDE "/home/amu5/users/georget/Phd/Simul/Defs/defs.inc"
#USE "/home/amu5/users/georget/Phd/Simul/library"


PROC NGen(CHAN OF BUNDLE FromDec1,ToCtrl2,ToDec1A,FromCtrl2A, VAL INT report)

  CHAN OF BUNDLE FromregA, ToregB, FromregBA:
  
  -----------------------------------------------------
  PROC RegA(CHAN OF BUNDLE Din, Dout, Ain, Aout)
    SEQ
      fifo.stage( Din, Dout, Ain, Aout)

  :
  -----------------------------------------------------
 
  PROC RegB(CHAN OF BUNDLE Din, Dout, Ain, Aout)
    SEQ
      last.fifo.stage( Din, Dout, Ain, Aout)

  :
  ----------------------------------------
  PROC NGenctrl(CHAN OF BUNDLE FromregA, ToregB, VAL INT report)

    [MESGLEN]INT Ot,Ng:
    BOOL end:
    INT ireg,n, sel, in1,in2,in3,in4, clock:
    [32]BOOL Otb ,nb:
    [16]BOOL iregb:

    --------------------------------
    PROC nGenproc(INT ireg, a)
      INT c,j,i,temp,clock:

      SEQ
        c:=0
        j:=ireg
        SEQ  i=0 FOR 16
          SEQ
            temp:=((j>>i)/\1)
            IF
              temp=1
                SEQ
                  c:=c+1
              TRUE
                SKIP
        a:=((c-1)/\#F)
    :
    ---------------------------------            

    SEQ
      FromregA?Ot
      IF
        Ot[0]<>FINISH
          SKIP
        TRUE
          end:=TRUE

      WHILE end=FALSE
        SEQ
          clock:=Ot[TIME.STAMP]+SELECT
          n:=0
          int.to.bool(n, nb)
  
          int.to.bool(Ot[0],Otb)
          IF
            Otb[4]=TRUE
              SEQ
                iregb:=[Otb FROM 5 FOR 16]
                init.hex(ireg, iregb)
                nGenproc(ireg, n)
                int.to.bool(n,nb)
                clock:=(clock+NGEN.DELAY.INT)+XOR
            TRUE
              SEQ
                clock:=clock+XOR
                SKIP 
    
          init.hex(sel, [Otb[3], Otb[4]])
          init.hex(in1, [VDD,VDD,VSS,VSS,VSS,VSS])
          init.hex(in2, [VSS,VSS,Otb[0],Otb[1],Otb[2],VSS])
          init.hex(in3, [VSS,VSS,nb[0],nb[1],nb[2],nb[3]])
          init.hex(in4, [VDD,VDD,nb[0],nb[1],nb[2],nb[3]])
          mux4(sel,in1,in2,in3,in4,Ng[0])
          Ng[TIME.STAMP]:=clock
          Ng[TIME.IN]:=Ot[TIME.IN]
          Ng[STALL]:=Ot[STALL]

          ToregB!Ng
          FromregA?Ot
          IF
            Ot[0]<>FINISH
              SKIP
            TRUE
              end:=TRUE
      ToregB!Ot
          
     

  :
  ------------------------------------------------------------
  SEQ      
    PAR
      RegA(FromDec1,FromregA, ToDec1A, FromregBA)
      NGenctrl(FromregA, ToregB, report)
      RegB(ToregB, ToCtrl2, FromregBA, FromCtrl2A)
      
:
  
