FromRegA, FromRegB,ToRegack: From Register Bank Olatch to 
                     Decode2(Ctrl2) / ack back to Olatch


FWCtrlD,FWCtrlC,FRegBA: From Write control to Register bank. D to be written
                 to a register and C for control(valid and ma)/Ack
                 back from Reg bank


ToApipe,FromApipe: Data from Decode2 to Apipe / Ack from Apipe

ToDatIntBw,ToDatIntMb,FDatIntAc: From Decode2(Ctrl2) to 
                        DatInt(Dout module) / ack from DatInt

FromCPsrA,ToCPsr: From Decode2(Ctrl2) to Decode3(CPreg) / ack back

FromOplat,ToOplatB,ToOplatA: From Decode2(Ctrl2) to Decode3(OPreg) / Ack back

FromImm,ToImm : From ImmPipe to Decode2(Ctrl2)/ Ack back

Dec1NG,NGDec1A: From Dec1 to Decode2(NGen) / ack back from NGen

Dec1Dec2,Dec2Dec1A: From Dec1 to Decode2(Dec2) / ack back from Dec2

Ctrl3Alx: From Decode3(ctrl3) to Decode2(Ctrl2) contains the carry 
          for the shifter

FromDec1D, ToDec1A: From Dec1 to Decode3(Dec3) / ack from decode3

AIDabt0: Abort signal from Decode3(Ctrl3) to AddInt. 

ALUgo: from Decode3(Ctrl3) to Dec1

ToWrCtrlD1,ToWrCtrlD2,FWctrlA : From Decode3(RReg) to Write Control /ack back

ToAddInta,ToAddIntb,FAddIntA: From Write Control(Wreg) to AddInt(AddC-arbiter) 
                      carry W/Wc  /ack back from AddC.

FAdInWlx:Ack From AddInt(AddC) to Wctrl 

FDatInta,FDatIntb,ToDatIntA: From DatInt(Din-DW, DWc) To Write control
                             / Ack back to DatInt(Din).

IpToDec1a,IpToDec1b,Dec1ToIpA: From DatInt(Ipipe) to Dec1 - carry IN, Flo /Ack
                               from Dec1. This part of Dec1 has not been
                               implemented yet.

FAddIntD,FAddIntC,ToAddIntA: From AddInt To DatInt. Carry the address
                             and the corresponding control. These
                             are actually sent by the AddInt to the memory 
                             but they have to go through DatInt.

ToAddIntD,FrAddIntA: From Dec1 to AddInt(AddC)- the LSMP channel, carries
                     the Ntrm bit / Ack back from AddC.

Dec1toXPD,XPtoDec1A: From Dec1 to AddInt(Xpipe) -Ack from Xpipe back

PCToDec1,Dec1PCA: From AddInt(PC pipe) to Dec1 / Ack from Dec1. This part
                  of the Dec1 has not been implemented yet.

XLtoDec1D,Dec1XLA:From AddInt(X latch) to Dec1 / Ack from Dec1. This part
                  of the Dec1 has not been implemented yet.

ToRegBI, ToRegBPC, FromRGA: From Dec1 to Register Bank(I-Reg) -Instruction
                            and PC / Ack back from I-Reg

ToImmD,FromImmA: From Dec1 to Imm-Pipe / Ack back from Imm-Pipe.

FDec3PCp: Pcparity signal from Decode3(Ctrl3) to Dec1 (Dec1CtrlA)



--------------------------------------------------------------------
MemDabt0,MemDabt1 : Abort signals from memory to Decode3(Ctrl3)

AMemDabt1, AMemDabt0:Abort signals from memory to AddInt

MEMad, MEMd, MEMc, MEMa:From DatInt to Memory- ADDRESS, DATA AND CONTROL 
                        /Ack back from memory. 

MrrDin, MrrPAbtin, MrrAin: From memory to DatInt- Datain and prefetch Abort
                           /Ack back to Memory. 
                    








                     
